Y. Royter, P.R. Patterson, J.C. Li, K.R. Elliott, T. Hussain, M.F. Boag-O’Brien, J.R. Duvall,
M.C. Montes, D.A. Hitko, M. Sokolich, D.H. Chow and P.D. Brewer
HRL Laboratories LLC, Malibu, CA, 90265, USA; Phone: (310) 317-5548; Email: email@example.com
For the first time, technology capable of wafer-scale device-level integration of InP HBTs and CMOS has been developed. With this technology full simultaneous utilization of III-V device speed and CMOS circuit complexity is possible. Simple ICs and test structures have been fabricated, showing no significant CMOS or HBT degradation and high heterogeneous interconnect yield. Resulting circuits maintain maximum CMOS integration density and HBT performance, while keeping the heterogeneous interconnect length below 5μm.