pHEMT Switch Yield Improvement Through Feedback From 100% Die Test

M. C. Tua, Paul Yeha, S. M. Liua, H. Y. Uengb and W. D. Changa

aWIN Semiconductors Corp, Kuei Shan Hsiang, Tao Yuan Shien, 333, R.O.. bDepartment of Electrical Engineering, National Sun Yat-Sen University, Kaoshiung 804 Taiwan E-mail: yadou@winfoundry.com

Keywords: lithography, gate lag, transient time

ABSTRACT
Yield improvement is an ongoing process in the MMIC production line. The gate lithography process will determine the major part of pHEMT wafer yield. This paper investigates yield improvement through feedback from automatic 100% DC and switching time on wafer testing. The breakdown and time domain test provides a reticle-dependent distribution pattern. This is photolithography process dependent and has been attributed to defocus during stepper exposure at gate level. Feeding this information back to the process engineers enables them to pinpoint the specific process step and improve the process yield.

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