Surface topography and overburden variation are encountered during Gallium Arsenide (GaAs) device manufacturing processes and have a significant impact on device performance and yield. A planarization process, CONTACT^® planarization, is presented to locally and globally planarize GaAs heterojunction bipolar transistor (HBT) wafers coated with polyimide material. This planarization process involves physically forcing the flowable material from the raised into the recessed areas to create a planar surface. As a result, the surface topography and overburden variation are significantly reduced, and broader processing latitudes are secured for downstream processes. Consequently, easier process control, more consistent device performance, and higher yield can be achieved.