Beyond CMOS: Logic Suitability of In_0.7Ga_0.3As HEMT

Dae-Hyun Kim and Jesús A. del Alamo

Massachusetts Institute of Technology, Cambridge, MA 02139, USA, 617-258-5752, vtsrc3@mtl.mit.edu

Keywords: HEMT, logic, subthreshold slope (S), DIBL, I_ON/I_OFF, gate delay (CV/I)

ABSTRACT

We have fabricated 100 nm InAlAs/InGaAs HEMTs that feature a tunneling cap designed to minimize parasitic resistance. We have characterized these devices from the point of logic, studying figures of merit such as gate delay (CV/I), subthreshold slope (S), drain-induced barrier lowering (DIBL), and I_ON/I_OFF. We have found that these devices exhibit promising logic characteristics. In particular, 100 nm L_g devices yield DIBL as low as 80 mV/V, S of 77 mV/decade, and I_ON/I_OFF ratio in excess of 10³ with a gate delay of about 1.2 ps. We have also found that these devices, from a logic application point of view, at 100 nm gate length have reached their scaling limit. Realizing the logic potential of In_0.7Ga_0.3As HEMTs will require a more scalable device design with better electrostatic integrity. If this can be accomplished, InGaAs HEMTs could well be the technology of choice when the CMOS roadmap comes to end.

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