Sub 100nm T-Gate Uniformity in InP HEMT Technology

 

D.A.J. Moran, E. Boyd, F. McEwan, H. McLelland, C.R. Stanley, I.G. Thayne

 

Ultrafast Systems Group, Nanoelectronics Research Centre,

Dept. of Electronics and Electrical Engineering,

The University of

Gawgow, Glasgow, G12 8QQ

Email: d.moran@elec.gla.ac.uk Tel: +44 (0) 141 330 6131

 

Keywords: HEMT, sub100nm, T-gate, non-annealed, uniformity, self-aligned

 

Abstract

This work describes the improved uniformity of short gate length (sub100nm) T-gate lithography observed for InP HEMT devices through the development of a non-annealed ohmic contact process.  The incorporation of such a process allows the reversal of ohmic and gate levels as part of a standard device process flow.  This eliminates fluctuations in the gate geometry that result from the spinning of gate resists across a non-planar surface i.e. between the source and drain contacts.

 

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