Novel Via Planarization Scheme for High Resolution Backside Wafer Processing

Hooman Kazemi, Lan Tran, H. Xin, Don Deakin, Judi Greer, Jonathan Hacker

Rockwell Scientific Company, 1049 Camino Dos rios, Thousand Oaks, CA  91360  (e-mail: hkazemi@rwsc.com).

 

Keywords: Substrate Via, Electromagnetic Crystal technology (EMXT), Inductively coupled plasma etching (ICP), planarization, Source via, PHEMT, power amplifiers, MMICs.

 

Abstract

Backside wafer planarization methods are discussed in GaAs substrates.  First method uses an epoxy based polymer to fill 10 mils deep via structures while the second method demonstrates a solidly filled 3.5mils deep metal vias.  The planarization step is accomplished with a lapping and polishing step which exposes the via connection to the frontside.  As a result high definition photolithography is made possible on the backside of the wafer normally compromised by the existence of the via structures.  A monolithic circuit is fabricated with greater than 10mil deep via structures.  The circuit is planarized using the epoxy technique and electrical contact is made through stripes in the frontside of the wafer.  Streets separated ground and signal paths on the backside of the wafer connecting to large area solder bumps.  The latter allows successful backside biasing of the frontside circuit with a planarized surface.

 

 

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